#ETHERNET MAC CONTROLLER DESIGN GENERATOR#
#ETHERNET MAC CONTROLLER DESIGN MANUAL#
#ETHERNET MAC CONTROLLER DESIGN VERIFICATION#

If everything works as expected, the last output line should read MAC functional check ended OK. $ make prepare ISE_DIR=/path/to/14.7/ISE_DS/ISE

#ETHERNET MAC CONTROLLER DESIGN VERIFICATION#

If you have GHDL and make installed, you can start a basic functional verification in a behavioral simulation of the core by simply running The source code includes the self-checking testbench entity ethernet_mac_tb. Run the 'Regenerate All Cores' process under 'Design Utilities'.Select the root node 'xc6slx45-2fgg484' in the hierarchy view.Open the project file ethernet_mac.xise in the ISE project navigator.In preparation for both running the testbench and using the MAC in a project, please follow these steps: Using the core currently requires an installation of Xilinx ISE 14.7 (WebPack will work) for the TX FIFO generation. Reduced gigabit media-independent interface (RGMII) support.

#ETHERNET MAC CONTROLLER DESIGN GENERATOR#

Replacement of the TX FIFO that is currently generated by the Xilinx core generator with a custom VHDL implementation.

#ETHERNET MAC CONTROLLER DESIGN MANUAL#

Manual link speed configuration via MIIM.Runtime configuration of core features and parameters.On-chip buses (can be integrated with custom code if needed).CSMA/CD (which effectively means no half-duplex connections).Polls the current PHY link state and speed by reading the status and auto-negotiation registers.Configures the PHY auto-negotiation to use full-duplex modes only.Basic media-independent interface management (MIIM) interface support that:.MII/GMII hardware I/O setup for Xilinx Spartan 6 family FPGAs.Media-independent interface (MII) for 10/100 Mb/s and gigabit media-independent interface (GMII) connectivity.Simple 8 bit wide FIFO user interface with arbitrary clock domains for packet transmission and reception.MAC address insertion into source address of outgoing packets (only when the first source address byte in the packet stream is 0xFF).Filtering received packets by destination MAC address.Verification of received packets (preamble, size, frame check sequence).Generation of Ethernet preamble and frame check sequence on transmission.Achievable data rate very close to theoretical maximum.Full-duplex IEEE 802.3 communication on copper at 10 (10BASE-T), 100 (100BASE-TX), and 1000 (1000BASE-T) Mb/s physical link speed.More information on the design and implementation can be found in the design document at. This page is a short overview of the features and usage of the MAC. The user interface is comprised of two FIFOs with a 8-bit data bus for packet transmission and reception, respectively. It was verified on hardware on a Trenz Electronic GmbH TE0600 GigaBee micromodule with a TE0603 baseboard. The core fully works on Xilinx Spartan 6 family FPGAs only at the moment. Only essential Ethernet functionality is supported. Its main distinction is the focus on simplicity both in the external user interface and internal operation. This tri-mode full-duplex Ethernet MAC sublayer was developed in VHDL as an alternative to both commercial and free implementations for usage on FPGAs.

Ethernet mac controller design